搜索资源列表
irig
- irig-b 单片机 解析 MSP430系列单片机是集成度高、超低功耗的16位单片机。Cyclone系列芯片是Altera公司推出的低价格、RAM可达288 kb的高容量的FPGA。IRIG-B码广泛应用于靶场时间信息的传递和各系统的时间同步。详细介绍了IRIG-B码解码电路和调制电路的硬件设计。MSP430的软件采用C语言编写，使程序有很强的可移植性。-irig-b microcontroller MSP430 Microcontroller analysis are highly int
caiji1
- 利用两个双口ram做的乒乓操作，采集高速大容量数据，fpga写，arm读-Two dual-port ram to do the ping-pong operation, collecting high-speed large-capacity data, fpga write, arm reading
3ram_ram
- 程序实现了FPGA内部RAM之间的数据传输。采用了3片RAM+RAM的结构形式。已通过调试-Procedures to achieve the data transmission between the FPGA internal RAM. Uses 3 RAM+RAM structure. Has passed through debugging
lpm_ram
- 一个基于quartus的LPM_RAM例子，VHDL语言写的，通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
ramblock
- this program can work and drive with UT62256 Static RAM by a FPGA
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
fifo_ram
- 同步fifo， 基于FPGA的VHDL编程，已调试。-fifo-ram
read
- 在FPGA内部实现RAM块中数据的读出，简单方便。-Internal implementation in FPGA block RAM read data
ramtest
- 用verilog语言往内部FPGA的sram中读写数据，即把1—4写入ram的1—4的地址里-Verilog language within the FPGA with the sram to read and write data, that is 1-4, 1-4 to write the address in ram
chunchuqidesheji
- 在计算机系统中，一般都提供一定数量的存储器。在用FPGA实现的系统中，除可以使用FPGA本身提供的存储器资源外，还可以使用FPGA的外部扩充存储器。本实验要求设计一个32×8 RAM，如下图所示，它包含5位地址、8位数据口和一个写控制端口。-In the computer system, generally provide a certain amount of memory. FPGA implementation of the system in use, unless you can us
using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
- 在 Spartan-3 系列 FPGA 中将查找表用作分布式 RAM-using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
m_decoder
- 恢复以曼彻斯特编码格式输入的mdi信号成实际数据并存储在双端口RAM后以中断方式通知DSP读取数据，所需双端口RAM程序可以从相应的FPGA编译系统中产生-A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required du
m_encoder
- 将写入的数据用曼彻斯特码格式从meout口输出，所需内部存储单元可根据所使用不同的FPGA类型由相应的编译软件产生所需双端口RAM模块-The data will be written by Manchester code format from meout port output, the required internal storage unit can be used according to the different types of FPGA Compiler software f
vlsiram
- VHDL RAM 16 * 8 source code FPGA
MATLAB_HexToMif
- 将Hex格式的数据转成Mif格式，供FPGA搭建系统时初始化RAM.-Hex format data will be converted into Mif format for initialization when the FPGA set up the system RAM.
rea_wri_ram
- 用FPGA实现对RAM的读写，实现特定的功能-FPGA implementation of the RAM with read and write, to achieve a specific function
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
The-pulse-signal-generator
- 脉冲信号发生器：采用DDS技术实现脉冲信号的周期、脉冲宽度、幅值的数控调节。通过单片机与FPGA的并行通信技术将频率控制字及矩形脉冲数据传送给FPGA的双口RAM。模拟输出通道则将信号通过100MHz、8位D/A转换器将波形数据转换成模拟脉冲信号，最后通过高速运放构成的放大器放大，实现幅度连续可调。-The pulse signal generator: using the DDS technology to achieve the pulse signal cycles, pulse widt
RAMaddressGenerator
- 基于FPGA（EP2C5T144开发板）的RAM的地址发生器，初学者适用-Based on FPGA (EP2C5T144 development board) RAM address generator for beginners
RAM_test
- ADSPTS201相关程序，总线方式、DMA方式读写片外SDRM和FPGA内部RAM数据 -ADSPTS201 procedures, the bus mode, DMA mode and the FPGA to read and write chip internal RAM data SDRM